Quality, Performance, Value, and True Compatibility

What is the Lenz GmbH position on compatibility and conformance?

Lenz GmbH wishes to reaffirm to our customers and to the general model-railroading public our position on developing compatible NMRA DCC products and on the need for the independent testing performed by the NMRA.

One of the most attractive aspects of DCC is full and complete interchange of decoders amongst all manufacturers. This is what differentiates DCC from other vender unique control systems

Why did we give our technology to the NMRA DCC Working Group?

We joined the NMRA DCC effort and offered up at no cost the basis for the technology. We did this with the belief that developing a new standard for model railroad control was critical to the evolution of the hobby. Key to that concept is an agreement amongst the manufacturers not to compete at the basic track communication protocols (an area covered by the basic NMRA standards) but instead to compete with features, service, quality and price. Our new LE080XS is an example of the types of innovation and creativity we can achieve yet still stay 100% compatible with all NMRA DCC systems.

What happens when manufacturers choose to compete at the track communication level?

Recently there has been a lot of discussion about manufacturers adding their own "Flair" to their decoders, which in effect would make these proprietary features available on selected systems. This has raised the aspect of a return to vender unique products.

Building products that only work for our systems would be relatively easy for all DCC manufacturers to do. It takes a lot of extra effort to develop truly compatible products that conform to the NMRA Standards and Recommended Practices. Adding new features outside the existing Standards and RP would also be easy, as it removes the need to reach consensus on key issues across the industry. Anyone can build unique products, it takes a dedication to quality to build products that completely follow the NMRA Standards.

We are saddened that one manufacturer has now decided to compete at the track protocol level and market decoders with its own unique proprietary extensions. To maximize the benefits of these proprietary features you are locked out of a wide range of other NMRA DCC products.

What is Lenz's future path in the NMRA DCC compatibility question?

We wish to reaffirm our position and ensure our customers that we will continue to produce equipment that is fully compatible with all NMRA DCC systems and will continue to submit our products for independent testing through the NMRA. While our customers are no different than any other and would prefer have new products, even if compatibility is compromised, we will continue not to release products until adequate testing has been completed and our standards are met.

We believe strongly in multi-manufacturer DCC and will continue to do our part to provide our customers with the highest quality DCC products that are truly compatible and contain unparalleled performance at a very competitive price. Yes this means more work for us, but it also means great benefit to you the consumer as it guarantees you a wide choice of systems and decoders to choose from both now and into the future.

QUALITY IS MORE THAN JUST PLACING A DCC LABEL ON A DECODER

Lenz GmbH tests all of our decoders against the industry recognized NMRA test suite. This test suite has been independently verified a number of times and provides the basis for ensuring that compatibility can be assured both now and into the future. Testing to this suite is just one of the steps we go through to ensure you receiving a quality product. We also test our product to other manufacturer systems, beta test our product with a number of users of various systems before release, submit our product for independent NMRA testing and quality test EACH and EVERY decoder we produce before it leaves the factory.

Sample of Test Results for Our New Decoder the LE080XS

<Sun Oct 10 22:06:23 1999> STATUS Test software version B.2.15
Manufacturer: Lenz Model number: LE080XS Serial number: 10/8/99
--------------------------------
Noise injecting booster 5.76 Volts peak soar meter 2 V/usec rise/fall 5/5
25% noise at 100 KHz
--------------------------------

<Sun Oct 10 22:07:06 1999> STATUS Starting decoder tests, address 3, type L
<Sun Oct 10 22:07:06 1999> STATUS Beginning self tests
<Sun Oct 10 22:07:09 1999> STATUS Self tests passed
<Sun Oct 10 22:07:09 1999> STATUS PC high 100( 54), low 100( 57)
<Sun Oct 10 22:07:09 1999> STATUS PC 1 usec delay 1
<Sun Oct 10 22:07:09 1999> STATUS Starting Decoder test cycle 1
<Sun Oct 10 22:07:10 1999> STATUS Margin test for 1T clock, 10 preambles
1T Margin: Minimum 1T 80, Maximum 1T 142
<Sun Oct 10 22:15:50 1999> STATUS Duty cycle test for 1 clock, 10 preambles
1H Duty: Min 1H <= -29, Max 1H 14 from 58 nominal
<Sun Oct 10 23:48:18 1999> STATUS Starting clock <Decoder minimum>
- Clock 0T 180, 0H 90, 1T 104
Ramp: Tests 8; Passes 8, 100%
pre 10 idle 1: Tests 100; Passes 100, 100%
pre 10 idle 2: Tests 100; Passes 100, 100%
pre 12 idle 1: Tests 100; Passes 100, 100%
pre 15 idle 1: Tests 100; Passes 100, 100%
pre 15 idle 2: Tests 100; Passes 100, 100%
Addr: Tests 253; Passes 253, 100%
Bad bit: Tests 39; Passes 39, 100%
0T 180 0H 90: Tests 100; Passes 100, 100%
0T 11980 0H 90: Tests 100; Passes 100, 100%
0T 11980 0H 11890: Tests 100; Passes 100, 100%
0T 2560 0H 2460: Tests 100; Passes 100, 100%
0T 12000 0H 2460: Tests 100; Passes 100, 100%
0T 12000 0H 11900: Tests 100; Passes 100, 100%
<Mon Oct 11 04:35:58 1999> STATUS Truncate clock
- Clock 0T 200, 0H 100, 1T 116
Pre 10 Frag 37: Tests 2; Passes 2, 100% *
Pre 10 Frag 36: Tests 2; Passes 2, 100%
Pre 10 Frag 35: Tests 2; Passes 2, 100%
Pre 10 Frag 34: Tests 2; Passes 2, 100%
Pre 10 Frag 33: Tests 2; Passes 2, 100%
Pre 10 Frag 32: Tests 2; Passes 2, 100%
Pre 10 Frag 31: Tests 2; Passes 2, 100%
Pre 10 Frag 30: Tests 2; Passes 2, 100%
Pre 10 Frag 29: Tests 2; Passes 2, 100%
Pre 10 Frag 28: Tests 2; Passes 2, 100% *
Pre 10 Frag 27: Tests 2; Passes 2, 100%
Pre 10 Frag 26: Tests 2; Passes 2, 100%
Pre 10 Frag 25: Tests 2; Passes 2, 100%
Pre 10 Frag 24: Tests 2; Passes 2, 100%
Pre 10 Frag 23: Tests 2; Passes 2, 100%
Pre 10 Frag 22: Tests 2; Passes 2, 100%
Pre 10 Frag 21: Tests 2; Passes 2, 100%
Pre 10 Frag 20: Tests 2; Passes 2, 100%
Pre 10 Frag 19: Tests 2; Passes 2, 100% *
Pre 10 Frag 18: Tests 2; Passes 2, 100%
Pre 10 Frag 17: Tests 2; Passes 2, 100%
Pre 10 Frag 16: Tests 2; Passes 2, 100%
Pre 10 Frag 15: Tests 2; Passes 2, 100%
Pre 10 Frag 14: Tests 2; Passes 2, 100%
Pre 10 Frag 13: Tests 2; Passes 2, 100%
Pre 10 Frag 12: Tests 2; Passes 2, 100%
Pre 10 Frag 11: Tests 2; Passes 2, 100%
Pre 10 Frag 10: Tests 2; Passes 2, 100% *
Pre 10 Frag 9: Tests 2; Passes 2, 100% *
Pre 10 Frag 8: Tests 2; Passes 2, 100% *
Pre 10 Frag 7: Tests 2; Passes 2, 100% *
Pre 10 Frag 6: Tests 2; Passes 2, 100% *
Pre 10 Frag 5: Tests 2; Passes 2, 100% *
Pre 10 Frag 4: Tests 2; Passes 2, 100% *
Pre 10 Frag 3: Tests 2; Passes 2, 100% *
Pre 10 Frag 2: Tests 2; Passes 2, 100% *
Pre 10 Frag 1: Tests 2; Passes 2, 100% *
Pre 10 Frag 0: Tests 2; Passes 2, 100% *
<Mon Oct 11 04:43:53 1999> STATUS Prior test clock
- Clock 0T 200, 0H 100, 1T 116
<42 42 00> <pre 10> Tests 2; Passes 2, 100%
<42 42 00> <pre 11> Tests 2; Passes 2, 100%
<42 42 00> <pre 12> Tests 2; Passes 2, 100%
<42 42 00> <pre 13> Tests 2; Passes 2, 100%
<42 42 00> <pre 14> Tests 2; Passes 2, 100%
<42 42 00> <pre 15> Tests 2; Passes 2, 100%
<42 42 00> <pre 16> Tests 2; Passes 2, 100%
<42 42 00> <pre 17> Tests 2; Passes 2, 100%
<42 42 00> <pre 18> Tests 2; Passes 2, 100%
<42 42 00> <pre 19> Tests 2; Passes 2, 100%
<42 42 00> <pre 20> Tests 2; Passes 2, 100% <42 42 00> 0<pre 18> Tests 2; Passes 2, 100%
<42 42 00> 0<pre 19> Tests 2; Passes 2, 100%
<42 42 00> 0<pre 20> Tests 2; Passes 2, 100%
<42 42 00>1 <pre 10> Tests 2; Passes 2, 100%
<42 42 00>1 <pre 11> Tests 2; Passes 2, 100%
<42 42 00>1 <pre 12> Tests 2; Passes 2, 100%
<42 42 00>1 <pre 13> Tests 2; Passes 2, 100%
<42 42 00>1 <pre 14> Tests 2; Passes 2, 100%
<42 42 00>1 <pre 15> Tests 2; Passes 2, 100%
<42 42 00>1 <pre 16> Tests 2; Passes 2, 100%
<42 42 00>1 <pre 17> Tests 2; Passes 2, 100%
<42 42 00>1 <pre 18> Tests 2; Passes 2, 100%
<42 42 00>1 <pre 19> Tests 2; Passes 2, 100%
<42 42 00>1 <pre 20> Tests 2; Passes 2, 100%
<42 42 00>1 0<pre 10> Tests 2; Passes 2, 100%
<42 42 00>1 0<pre 11> Tests 2; Passes 2, 100%
<42 42 00>1 0<pre 12> Tests 2; Passes 2, 100%
<42 42 00>1 0<pre 13> Tests 2; Passes 2, 100%
<42 42 00>1 0<pre 14> Tests 2; Passes 2, 100%
<42 42 00>1 0<pre 15> Tests 2; Passes 2, 100%
<42 42 00>1 0<pre 16> Tests 2; Passes 2, 100%
<42 42 00>1 0<pre 17> Tests 2; Passes 2, 100%
<42 42 00>1 0<pre 18> Tests 2; Passes 2, 100%
<42 42 00>1 0<pre 19> Tests 2; Passes 2, 100%
<42 42 00>1 0<pre 20> Tests 2; Passes 2, 100%
<Mon Oct 11 04:56:45 1999> STATUS 6 byte prior test clock
- Clock 0T 200, 0H 100, 1T 116
<42 61 61 61 61 42> <pre 10> Tests 2; Passes 2, 100%
<42 61 61 61 61 42> <pre 11> Tests 2; Passes 2, 100%
<42 61 61 61 61 42> <pre 12> Tests 2; Passes 2, 100%
<42 61 61 61 61 42> <pre 13> Tests 2; Passes 2, 100%
<42 61 61 61 61 42> <pre 14> Tests 2; Passes 2, 100%
<42 61 61 61 61 42> 0<pre 10> Tests 2; Passes 2, 100%
<42 61 61 61 61 42> 0<pre 11> Tests 2; Passes 2, 100%
<42 61 61 61 61 42> 0<pre 12> Tests 2; Passes 2, 100%
<42 61 61 61 61 42> 0<pre 13> Tests 2; Passes 2, 100%
<42 61 61 61 61 42> 0<pre 14> Tests 2; Passes 2, 100%
<42 61 61 61 61 42>1 <pre 10> Tests 2; Passes 2, 100%
<42 61 61 61 61 42>1 <pre 11> Tests 2; Passes 2, 100%
<42 61 61 61 61 42>1 <pre 12> Tests 2; Passes 2, 100%
<42 61 61 61 61 42>1 <pre 13> Tests 2; Passes 2, 100%
<42 61 61 61 61 42>1 <pre 14> Tests 2; Passes 2, 100%
<42 61 61 61 61 42>1 0<pre 10> Tests 2; Passes 2, 100%
<42 61 61 61 61 42>1 0<pre 11> Tests 2; Passes 2, 100%
<42 61 61 61 61 42>1 0<pre 12> Tests 2; Passes 2, 100%
<42 61 61 61 61 42>1 0<pre 13> Tests 2; Passes 2, 100%
<42 61 61 61 61 42>1 0<pre 14> Tests 2; Passes 2, 100%

<Mon Oct 11 04:59:09 1999> STATUS Packets sent 1806818, Bytes sent 14407804
<Mon Oct 11 04:59:09 1999> STATUS Tests COMPLETED, All tests passed